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첨단 반도체 패키징 시장(2023-2033년)

Advanced Semiconductor Packaging 2023-2033

리서치사 IDTechEx Ltd.
발행일 2022년 08월 상품코드 1108021
페이지 정보 영문 444 Slides 배송안내 1-2일 (영업일 기준)
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첨단 반도체 패키징 시장(2023-2033년) Advanced Semiconductor Packaging 2023-2033
발행일 : 2022년 08월 페이지 정보 : 영문 444 Slides

본 상품은 영문 자료로 한글과 영문 목차에 불일치하는 내용이 있을 경우 영문을 우선합니다. 정확한 검토를 위해 영문목차를 참고해주시기 바랍니다.

우리의 미래를 한 마디로 특징 짓는다면, 그것은 바로 '데이터 중심적'일 것입니다.

오늘날 거의 모든 산업에서 데이터가 폭발적으로 증가하고 있습니다. 매초마다 우리의 디지털세계는 4,000 테라 바이트의 데이터를 생성하고 있으며 이 양은 미래에 더 증가할 것으로 예상됩니다.

기계 학습 및 AI와 같은 데이터가 풍부한 애플리케이션은 데이터 센터, 5G, 자율 주행 차량을 포함한 광범위한 애플리케이션에서 핵심 데이터를 제공합니다. 이러한 앱을 실행하기 위해서는 강력한 프로세스가 필요하며 그 중 기초는 Si를 기반으로 한 직접 회로(IC)입니다.

수십년 동안 인텔과 같은 IC공급 업체는 모든 기능이 동일한 동일한 다이에 통합된 칩을 설계할 것이지만 업계가 무어의 법칙(칩 밀도가 더 이상 2년마다 두 배로 증가하지 않음)의 둔화를 경험하면서 모놀리식(monolithic)IC를 확장하는 것이 점점 더 많은 비용이 들고 어려운 일임을 깨닫게 됩니다. 이로 인해 IC벤더들은 '첨단 반도체 패키징' 산업으로 나아가게 되었습니다.

첨단 반도체 패키징이란 무엇인가?

일반적으로 반도체 패키징은 반도체 장치를 제조하고 테스트를 거치는 마지막 두 단계의 과정입니다. IC를 예로 들자면 패키징 공정에서 IC베어 다이는 전기적 접촉이 있는 지지케이스에 캡슐화됩니다. 이러한 방식으로 케이싱은 IC베어 다이를 물리적 손상 및 부식으로부터 보호하고 IC를 다른 장치의 PCB보드에 연결합니다. 반도체 패키징은 수십 년 동안 존재해 왔으며 반도체 패키징의 첫 대량 생산은 1970년대 초에 이루어졌습니다.

앞서 언급했듯이 무어의 법칙의 둔화와 모놀리식 IC제조 비용의 증가로 인해, IC공급업체는 효율적인 비용 및 고성능 프로세서를 설계하는 데 새로운 접근 방식을 필요로 하게 되었습니다. 이에 '칩렛(chiplet)' 이라고 불리는 새로운 디자인은 앞으로 나아갈 주요 트렌드입니다.

칩렛에 숨겨진 아이디어는 모놀리식 IC를 여러 기능 블록으로 분할하고 기능 블록을 별도의 칩렛으로 재구성한 다음 패키지 수준에서 이들을 다시 조립하는 것입니다.

이상적으로 칩렛 설계를 기반으로 하는 프로세스는 모놀리식 IC보다 동일하거나 더 큰 성능을 갖지만 총 생산 비용은 낮아야 합니다. 패키징 방법, 특히 여러 칩렛을 연결하는 데 사용되는 방법은 시스템 전체에 영향을 미치기 때문에 칩렛 설계에 중요한 역할을 합니다.

2.5D IC, 3D IC 및 고밀도 팬아웃 웨이퍼 레벨 패키징을 포함한 이러한 패키징 기술은 "고급 반도체 패키징"으로 분류되며 이 보고서에서 우리의 연구 대상입니다. 이를 통해 단일 기판의 다양한 프로세스 노드에서 여러 칩릿을 병합할 수 있으며 범프 크기가 작아 상호 연결 밀도가 높아지고 통합 기능이 향상됩니다.

보고서 "Advanced Semiconductor Packaging 2023-2033"에는 첨단 반도체 패키징 기술의 최신 혁신, 주요 기술 동향, 가치 사슬 전반의 분석, 주요 플레이어 분석 및 세분화 된 시장 예측에 대한 자세한 조사가 포함됩니다.

첨단 반도체 패키징은 데이터 센터, 5G, 자율 주행 차량 및 가전 등 네 가지 주요 시장에서 활용될 차세대 IC의 중요한 토대 역할을 합니다. IDTechEx는 첨단 반도체 패키징의 영향력과 향후 미래 시장의 예측을 통해 다음의 내용을 제공합니다.

기술 동향 및 제조업체 분석

  • Si IC 산업에 대한 자세한 개요 - 기술 로드맵 및 플레이어 역학 포함
  • 반도체 IC 산업의 공급망 및 비즈니스 모델 분석
  • 다양한 반도체 패키징 기술 분석
  • 회사의 최첨단 기술 및 향후 연구 개발을 포함한 주요 기업의 첨단 반도체 패키징 기술에 대한 심층적 분석
  • 고급 반도체 패키징을 위한 주요 시장에 대한 자세한 개요. 고성능 컴퓨팅, 자율 주행 차량, 5G 및 가전 제품 포함 다양한 응용 분야에서 고급 반도체 패키징의 사용을 보여주는 수많은 사례 연구

IDTechEx가 연구한 네 가지 주요 시장(데이터 센터, 자율 주행 차량, 5G, 소비자 가전)에서 주요 첨단 반도체 패키징 기술(2.5D 임베디드 Si, 2.5Si 인터포저, 2.5D(Ultra) 고밀도 팬아웃, 3D 다이 스태킹 포함)의 시장 확장성을 조사합니다. 이 정보는 세분화된 시장 10개년 예측 및 분석으로 제공됩니다.

세분화된 시장 10개년 예측 및 분석

  • 데이터 센터 서버 : 단위 예측 2022-2033 (선적)
  • 데이터 센터 CPU: 첨단 반도체 패키징 유닛 예측 2022-2033 (출하)
  • 데이터 센터 가속기: 첨단 반도체 패키징 유닛 예측 2022-2033 (출하)
  • L4+ 자율주행차용 2.5D 첨단 반도체 패키징 유닛 매출 전망 2022-2045
  • L4+ 자율주행차의 3D 첨단 반도체 패키징 유닛 판매 전망 2022-2045
  • 스마트폰/태블릿/스마트워치/AR/VR/MR 등 가전제품 판매량 전망 2022-2033

목차

1. 요약

  • 1.1. 일반 전자 포장 - 개요
  • 1.2. 고급 반도체 패키징 - 개요
  • 1.3. 고급 반도체 패키징 기술 - 당사의 범위
  • 1.4. 반도체 패키징 - 기술 개요
  • 1.5. 1D에서 3D 반도체 패키징으로
  • 1.6. 첨단 반도체 패키징의 부상과 도전 과제
  • 1.7. 첨단 반도체 패키징 기술을 위한 네 가지 핵심 동인
  • 1.8. 첨단 반도체 패키징 기술의 장점 핵심 인물
  • 1.9. 주요 시장의 포장 동향
  • 1.10. 고급 반도체 패키징 및 솔루션 분야의 선수
  • 1.11. 지리학별 고급 반도체 패키징 업체
  • 1.12. HPC 칩 공급망 분석
  • 1.13. 첨단 반도체 패키징 기술을 기반으로 한 고급 상용 칩 (1)
  • 1.14. 첨단 반도체 패키징 기술을 기반으로 한 고급 상용 칩 (2)
  • 1.15. 기업별 첨단 반도체 패키징에 대한 투자
  • 1.16. 반도체 파운드리 및 로드맵
  • 1.17. IC 산업의 비즈니스 가치 사슬
  • 1.18. IC 산업의 생태계/비즈니스 모델
  • 1.19. 칩렛 서버 CPU의 향후 패키징 동향
  • 1.20. 데이터 센터 서버 유닛 예측 2022-2033 (선적)
  • 1.21. 총 주소 지정 가능한 데이터 센터 CPU 시장 전망 2022-2033 (출하)
  • 1.22. 데이터 센터 CPU : 고급 반도체 패키징 유닛 예측 2022-2033 (선적)
  • 1.23. 미래의 ADAS/자율 주행 시스템: 요구 사항, 조치 및 현재 과제
  • 1.24. 자동차 전자 장치의 세 가지 변형 기둥
  • 1.25. L4+ 자율주행차 판매 전망 2022-2045
  • 1.26. L4+ 자율주행차의 총 주소 지정 가능한 ADAS 프로세서 및 액셀러레이터 판매 시장 전망 2022-2045
  • 1.27. L4+ 자율주행차 2.5D 첨단 반도체 패키징 유닛 판매 전망 2022-2045
  • 1.28.3D L4+ 자율주행차의 첨단 반도체 패키징 유닛 판매 전망 2022-2045
  • 1.29. 스마트폰/태블릿/스마트워치/AR/VR/MR 단위 판매 전망 2022-2033
  • 1.30. 2022-2033년 가전제품 APE(어플리케이션 프로세서 환경)에 대한 첨단 반도체 패키징 유닛 전망 (1)
  • 1.31. 가전제품 APE(어플리케이션 프로세서 환경)에 대한 첨단 반도체 패키징 유닛 전망 2022-2033 (2)
  • 1.32. 2022-2033년 글로벌 PC 출하 전망
  • 1.33. PC 전망 2022-2033의 고급 반도체 패키징 유닛 (1)
  • 1.34. PC 전망 2022-2033의 고급 반도체 패키징 유닛 (2)
  • 1.35. MIMO 사이즈 유닛별 5G 라디오 2022-2032년 전망 (누적)
  • 1.36. 5G RAN 인프라 2022-2032의 첨단 반도체 패키징 시장 전체 주소 지정 가능 시장 추정 (누적)
  • 1.37. 5G RAN 네트워크를 위한 고급 반도체 패키징 유닛 2022-2032 (누적)
  • 1.38. 요약
  • 1.39. 회사 프로필

2. 소개

3. 다양한 플레이어의 첨단 반도체 패키징 기술에 대한 기술 심층 분석

4. 첨단 반도체 포장 : 공급망 및 플레이어

5. 다른 시장을 위한 첨단 반도체 패키징

6. 시장 예측

  • 6.1. 데이터 센터 서버 유닛 예측 2022-2033 (선적)
  • 6.2. 총 주소 지정 가능한 데이터 센터 CPU 시장 전망 2022-2033 (출하)
  • 6.3. 데이터 센터 CPU : 고급 반도체 패키징 유닛 예측 2022-2033 (선적)
  • 6.4. 총 주소 지정 가능한 데이터 센터 액셀러레이터 시장 전망 2022-2033 (선적)
  • 6.5. 데이터 센터 가속기 : 고급 반도체 패키징 유닛 예측 2022-2033 (선적)
  • 6.6. 미래의 ADAS/자율 주행 시스템: 요구 사항, 조치 및 현재 과제
  • 6.7. 자동차 전자 장치의 세 가지 변형 기둥
  • 6.8. L4+ 자율주행차 판매 전망 2022-2045
  • 6.9. L4+ 자율주행차의 총 주소 지정 가능한 ADAS 프로세서 및 액셀러레이터 판매 시장 전망 2022-2045
  • 6.10. L4+ 자율주행차 2.5D 첨단 반도체 패키징 유닛 매출 전망 2022-2045
  • 6.11.3D L4+ 자율주행차의 첨단 반도체 패키징 유닛 판매 전망 2022-2045
  • 6.12. 스마트폰/태블릿/스마트워치/AR/VR/MR 단위 판매 전망 2022-2033
  • 6.13. 2022-2033년 가전제품 APE(응용 프로세서 환경)에 대한 첨단 반도체 패키징 유닛 전망 (1)
  • 6.14. 가전제품 APE(어플리케이션 프로세서 환경)에 대한 첨단 반도체 패키징 유닛 전망 2022-2033 (2)
  • 6.15. 2022-2033년 글로벌 PC 출하 전망
  • 6.16. PC 예측의 고급 반도체 패키징 유닛 2022-2033 (1)
  • 6.17. PC 예측의 첨단 반도체 패키징 유닛 2022-2033 (2)
  • 6.18. MIMO 사이즈 유닛별 5G 라디오 2022-2032년 전망 (누적)
  • 6.19. 5G RAN 인프라 2022-2032의 첨단 반도체 패키징 시장 전체 주소 지정 가능 시장 추정 (누적)
  • 6.20. 5G RAN 네트워크를 위한 고급 반도체 패키징 유닛 2022-2032 (Cumulative)
BHI 22.08.03

Title:
Advanced Semiconductor Packaging 2023-2033
Heterogeneous integration; AI; high performance computing (HPC); data centers; autonomous vehicles; 5G; semiconductor packaging market forecasts; 2.5D IC packaging; 3D IC packaging; antenna in package (AiP).

Advanced packaging - a critical foundation for next-generation ICs.

Paving the way to the data-centric future

If we were to characterize our future in one word, it would be "data-centric".

Today, there is an explosion of data at every level and in almost every industry. Every second, our digital world generates 4,000 terabytes of data, and this amount is only expected to go up, if not considerably, in the future.

Data-rich applications such as machine learning and AI are the key data enablers in a wide range of applications including data centers, 5G, autonomous vehicles. To run these apps, a powerful processor is required, of which the foundation is an integrated circuit (IC) built on Si.

For decades, IC vendors such as Intel would design a chip that has all functions integrated on the same die, however, as the industry sees the slowdown of Moore's law (the chip densities are no longer doubling every two years), scaling monolithic IC becomes more and more difficult and costly. This pushes IC vendors toward "advanced semiconductor packaging."

What is advanced semiconductor packaging?

                            Source: Advanced semiconductor packaging 2023-2033

Generally speaking, semiconductor packaging is the last two steps of manufacturing a semiconductor device followed by testing. Taking packaging an IC as an example, in the packaging process, the IC bare die is encapsulated in a supporting case with electrical contacts. In this way, the casing protects the IC bare die from physical harm and corrosion and links the IC to a PCB board to other devices. Semiconductor packaging has existed for decades - the first volume production of semiconductor packaging came in the early 1970s. So, what is new?

As mentioned, due to the slowdown of Moore's law and significant increases in the cost of manufacturing a monolithic IC, IC vendors required new approaches to designing processors that enable high performance and at the same time remaining cost-effective. A new design, called a "chiplet", is the key trend going forwards.

The idea behind chiplets is to "split" a monolithic IC into multiple functional blocks, reconstitute the functional blocks into separate chiplets, and then "re-assemble" these at the package level. Ideally, a processor based on chiplet design should have the same or greater performance but lower total production costs than monolithic IC. Packaging methods, particularly those used to link several chiplets, play a crucial role in chiplet design since they affect the system's performance as a whole. These packaging technologies, including 2.5D IC, 3D IC, and high-density fanout wafer level packaging, are categorised as "advanced semiconductor packaging" and are the subject of our research in this report. They allow for the merging of multiple chiplets at various process nodes on a single substrate and to have small bump sizes to enable higher interconnect densities and higher integration capabilities.

What is in this report?

This report "Advanced Semiconductor Packaging 2023-2033" includes detailed examination of the latest innovations in advanced semiconductor packaging technology, key technical trends, analysis across the value chain, major player analysis, and granular market forecasts. Furthermore, this study gives a comprehensive evaluation of the semiconductor industry in general.

Advanced semiconductor packaging serves as a critical foundation for next generation ICs that will be utilized in four key markets: data centers, 5G, autonomous vehicles, and consumer electronics. IDTechEx leverages its expertise in these sectors to provide the reader with a thorough understanding of how advanced semiconductor packaging is influencing these fields and what the future may hold.

Below we list key aspects of this report:

Technology trends & manufacturer analysis

  • Detailed overview of Si IC industry - including technology roadmap and player dynamics
  • Analysis of supply chain and business model in the semiconductor IC industry
  • Analysis of different semiconductor packaging technologies
  • In-depth analysis of key companies' advanced semiconductor packaging technologies - including the companies' state-of-the-art technology and future research development
  • Detailed overview of key markets for advanced semiconductor packaging. Including high-performance computing, autonomous vehicles, 5G, and consumer electronics
  • Numerous case studies demonstrating the use of advanced semiconductor packaging in a variety of applications.

In this report, IDTechEx also examines the market scalability of key advanced semiconductor packaging technologies (including 2.5D embedded Si, 2.5 Si interposer, 2.5D (Ultra) high density fanout, and 3D die stacking) in the four primary markets (Data center, Autonomous vehicles, 5G, Consumer electronics) studied by IDTechEx. This information is translated into 10-year granular market forecasts & analysis.

10-year granular market forecasts & analysis

  • Data Center Server: unit forecast 2022-2033 (Shipment)
  • Data Center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment)
  • Data Center Accelerator: advanced semiconductor packaging unit forecast 2022-2033 (Shipment)
  • 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045
  • 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045
  • Unit sales forecast for consumer electronics including smartphones/tablets/smartwatches/AR/VR/MR 2022-2033

Analyst access from IDTechEx

All report purchases include up to 30 minutes telephone time with an expert analyst who will help you link key findings in the report to the business issues you're addressing. This needs to be used within three months of purchasing the report.

TABLE OF CONTENTS

1. EXECUTIVE SUMMARY & CONCLUSIONS

  • 1.1. General electronic packaging - an overview
  • 1.2. Advanced semiconductor packaging - an overview
  • 1.3. Advanced semiconductor packaging technologies - Our scope
  • 1.4. Semiconductor packaging - an overview of technology
  • 1.5. From 1D to 3D semiconductor packaging
  • 1.6. The rise of advanced semiconductor packaging and its challenges
  • 1.7. Four key drivers for advanced semiconductor packaging technologies
  • 1.8. Key figures of merit of advanced semiconductor packaging technologies
  • 1.9. Packaging trend for key markets
  • 1.10. Players in advanced semiconductor packaging and their solutions
  • 1.11. Players in advanced semiconductor packaging by geography
  • 1.12. HPC chip supply chain analysis
  • 1.13. High-end commercial chips based on advanced semiconductor packaging technology (1)
  • 1.14. High-end commercial chips based on advanced semiconductor packaging technology (2)
  • 1.15. Investment in advanced semiconductor packaging by companies
  • 1.16. Semiconductor foundries and their roadmap
  • 1.17. Business value chain in IC industry
  • 1.18. Ecosystem/Business model in the IC industry
  • 1.19. Future packaging trend for chiplet server CPU
  • 1.20. Data Center Server Unit Forecast 2022-2033 (Shipment)
  • 1.21. Total addressable data center CPU market forecast 2022-2033 (Shipment)
  • 1.22. Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment)
  • 1.23. Future ADAS/Autonomous driving systems: requirements, actions, and current challenges
  • 1.24. Three transformational pillars in automotive electronics
  • 1.25. L4+ Autonomous vehicles sales forecast 2022-2045
  • 1.26. Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045
  • 1.27. 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045
  • 1.28. 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045
  • 1.29. Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033
  • 1.30. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1)
  • 1.31. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2)
  • 1.32. Global PC shipment forecast 2022-2033
  • 1.33. Advanced semiconductor packaging units in PC forecast 2022-2033 (1)
  • 1.34. Advanced semiconductor packaging units in PC forecast 2022-2033 (2)
  • 1.35. 5G radios by MIMO size unit forecast 2022-2032 (Cumulative)
  • 1.36. Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative)
  • 1.37. Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative)
  • 1.38. Summary
  • 1.39. Company profiles

2. INTRODUCTION

  • 2.1. Si IC: technology trend
  • 2.2. Paving the way to the data-centric future
  • 2.3. Fundamentals of abundance data computing system
  • 2.4. Key parameter of growth for processor and memory (1)
  • 2.5. Key parameter of growth for processor and memory (2)
  • 2.6. Memory bandwidth deficit
  • 2.7. Four key area of growth for abundance data computing system
  • 2.8. The economics of scaling
  • 2.9. Scaling technology roadmap overview
  • 2.10. Transistor device development (1)
  • 2.11. Transistor device development (2)
  • 2.12. Key parameters for transistor device scaling
  • 2.13. Evolution of transistor device architectures
  • 2.14. CNTs for transistors
  • 2.15. CNFET research breakthrough (1)
  • 2.16. CNFET research breakthrough (2)
  • 2.17. CNFET case study (1)
  • 2.18. 3D SOC
  • 2.19. On-chip memory
  • 2.20. Routes to increase I/O density
  • 2.21. Si IC players analysis - research and manufacturing roadmap
  • 2.22. Roadmap of pioneering companies in Si advanced process node
  • 2.23. The players in Si advanced process node
  • 2.24. TSMC (1)
  • 2.25. TSMC (2)
  • 2.26. TSMC (3)
  • 2.27. TSMC (4)
  • 2.28. Intel (1)
  • 2.29. Intel (2)
  • 2.30. Intel (3)
  • 2.31. Samsung (1)
  • 2.32. Samsung (2)
  • 2.33. Semiconductor foundries and their roadmap
  • 2.34. Advanced semiconductor packaging technologies - introduction and technology trend
  • 2.35. General electronic packaging - an overview
  • 2.36. Advanced semiconductor packaging - an overview
  • 2.37. Semiconductor packaging - an overview of technology
  • 2.38. From 1D to 3D semiconductor packaging
  • 2.39. The rise of advanced semiconductor packaging and its challenges
  • 2.40. Four key drivers for advanced semiconductor packaging technologies
  • 2.41. Key figures of merit of advanced semiconductor packaging technologies
  • 2.42. Packaging trend for key markets
  • 2.43. Advanced semiconductor packaging technologies - our scope
  • 2.44. Business value chain in IC industry
  • 2.45. Ecosystem/Business model in the IC industry
  • 2.46. Role and advantages of players in advanced semiconductor packaging market
  • 2.47. Heterogeneous integration solutions
  • 2.48. Heterogeneous integration solutions
  • 2.49. System on Chip (SOC)
  • 2.50. System on Chip (SOC) (2)
  • 2.51. Multi-Chip Module (MCM)
  • 2.52. System in Package (SIP)
  • 2.53. System on Package (SOP)
  • 2.54. Comparison between SIP and SOP
  • 2.55. PCB-Embedding Technology
  • 2.56. PCB Embedding Technology - Active Chips
  • 2.57. PCB Embedding Technology - Active Chips (continued)
  • 2.58. PCB Embedding Technology - Cases
  • 2.59. PCB Embedding Technology - Cases (continued)
  • 2.60. Chip Embedding Technologies (CET) - Integrated Passive Device
  • 2.61. Packaging technologies by interconnect technique
  • 2.62. Interconnection technique
  • 2.63. Interconnection technique - Wire Bond
  • 2.64. Interconnection technique - Flip Chip
  • 2.65. Interconnection technique - Wafer level packaging
  • 2.66. Fan-out process flow
  • 2.67. Interconnection technique - Interposer
  • 2.68. Interposer Structure
  • 2.69. Passive vs Active Interposer
  • 2.70. Interposer alternative - Bridge
  • 2.71. Interconnection technique - Technology benchmark
  • 2.72. Die/Package stacking technologies
  • 2.73. Die/Package stacking technologies - an overview
  • 2.74. Package in Package (PIP) vs Package on Package (POP)
  • 2.75. Die stacking
  • 2.76. Differences between stacked packages and stacked dies
  • 2.77. 2.5D and 3D IC Packaging
  • 2.78. 2.5D IC Packaging
  • 2.79. 3D IC Packaging technology
  • 2.80. 3D IC Packaging

3. TECHNOLOGICAL DEEP DIVE INTO ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES FROM VARIOUS PLAYERS

  • 3.1. Overview
    • 3.1.1. Players in advanced semiconductor packaging and their solutions
  • 3.2. TSMC's advanced semiconductor packaging solutions
    • 3.2.1. TSMC 3DFabricTM packaging technologies overview
    • 3.2.2. TSMC 2.5D packaging technology - CoWoS
    • 3.2.3. TSMC 2.5D packaging technology - InFO
    • 3.2.4. TSMC INFO technology - process flow
    • 3.2.5. TSMC 2.5D packaging technology applications
    • 3.2.6. TSMC 2.5D packaging technologies roadmap
    • 3.2.7. TSMC 3D SoIC Technology
    • 3.2.8. TSMC 3D SoIC development roadmap
    • 3.2.9. Why scaling bump/bond pitch size is important?
    • 3.2.10. Process of "bumpless" bonding - Cu bonding technologies
    • 3.2.11. How bonding pitch size affects system performance
    • 3.2.12. Roadmap of bond pitch scaling
    • 3.2.13. Future high band width memory using SoIC technology
    • 3.2.14. Thermal management for SoIC
    • 3.2.15. Technology benchmark between 2.5D, 3D-IC, and SoIC
    • 3.2.16. Combine 3D SoIC and 2.5D backend packaging technologies
    • 3.2.17. N3XT Solution: 3D Monolithic integration
    • 3.2.18. TSMC considers Packaging Facility in the US
    • 3.2.19. Intel's advanced semiconductor packaging solutions
    • 3.2.20. Intel advanced IC packaging profile
    • 3.2.21. Intel Packaging technology roadmap
    • 3.2.22. Intel EMIB (Embedded Multi-Die interconnect Bridge)
    • 3.2.23. Products that use EMIB technology
    • 3.2.24. EMIB Process flow
    • 3.2.25. EMIB - power distribution path
    • 3.2.26. EMIB key parameters
    • 3.2.27. EMIB roadmap - bump size reduction
    • 3.2.28. Intel Ponte Vecchio package teardown
    • 3.2.29. Intel 3D Foveros
    • 3.2.30. Intel 3D Foveros roadmap
    • 3.2.31. Intel 3D Foveros ODI
    • 3.2.32. Intel 3D Foveros Direct
    • 3.2.33. Three key interconnect breakthrough from Intel
    • 3.2.34. Intel interconnect technology - hybrid bonding
    • 3.2.35. Intel interconnect technology - Zero Misaligned Via (ZMV)
    • 3.2.36. Intel 3D packaging roadmap: Co-EMIB (2.5D+3D)
    • 3.2.37. Intel Lakefield advanced semiconductor packaging
    • 3.2.38. Intel's products that are/will be using 3D Foveros
  • 3.3. SPIL's advanced semiconductor packaging solutions
    • 3.3.1. SPIL Fan-Out Embedded Bridge (FOEB) Technology
    • 3.3.2. SPIL FOEB Technology process flow
    • 3.3.3. SPIL FOEB - Thermal and Warpage
    • 3.3.4. SPIL FOEB vs 2.5D
    • 3.3.5. SPIL FOEB vs Intel EMIB
  • 3.4. Samsung's advanced semiconductor packaging solutions
    • 3.4.1. Samsung advanced IC packaging profile
    • 3.4.2. Samsung's advanced semiconductor packaging solutions
    • 3.4.3. Samsung's technology roadmap for HPC
    • 3.4.4. Samsung's advanced semiconductor packaging solutions for HPC
    • 3.4.5. Samsung's X-Cube and I-Cube4 packaging schematic
    • 3.4.6. Samsung RDL-first fan-out wafer level package (FOWLP) process flow
    • 3.4.7. Samsung next generation high bandwidth memory: HBM3
    • 3.4.8. Samsung H-Cube advanced semiconductor packaging technology
  • 3.5. Amkor's advanced semiconductor packaging solutions
    • 3.5.1. Overview
    • 3.5.2. Amkor's 2.5D TSV FCBGA
    • 3.5.3. Summary of Amkor's 2.5D TSV technologies
    • 3.5.4. Stacked substrate (2.5D packaging) from Amkor
    • 3.5.5. High-Density Fan-Out (HDFO) solution from Amkor
    • 3.5.6. Amkor's S-SWIFT packaging solution (1)
    • 3.5.7. Amkor's S-SWIFT packaging solution (2)
    • 3.5.8. Amkor - RDL layers development
    • 3.5.9. Electrical characteristics vs different RDL solution
    • 3.5.10. Amkor's S-SWIFT package development status
    • 3.5.11. Amkor - 3D stacking
    • 3.5.12. Amkor - Cu-Cu Hybrid bonding pathfinding on the way
  • 3.6. ASE's advanced semiconductor packaging solutions
    • 3.6.1. ASE 2.5D technologies - FOCoS
    • 3.6.2. ASE FOCoS process flow (1)
    • 3.6.3. ASE FOCoS process flow (2)
    • 3.6.4. Pros and Cons of FOCoS chip last
    • 3.6.5. ASE FOCoS chip last package characteristic
  • 3.7. IMEC advanced semiconductor packaging solution
    • 3.7.1. Imec's Flip Chip on FOWLP
    • 3.7.2. Flip Chip on FOWLP - Process flow
    • 3.7.3. Flip Chip on FOWLP - challenges
    • 3.7.4. 3D Integration technology landscape

4. ADVANCED SEMICONDUCTOR PACKAGING - SUPPLY CHAIN AND PLAYERS

  • 4.1. Overview
    • 4.1.1. Players in advanced semiconductor packaging by geography
    • 4.1.2. HPC chip supply chain analysis
    • 4.1.3. Investment in advanced semiconductor packaging by companies
  • 4.2. Chiplet
    • 4.2.1. What is chiplet technology
    • 4.2.2. Why chiplet technology
    • 4.2.3. Benefits of chiplet
    • 4.2.4. AMD Chiplet performance vs cost
    • 4.2.5. Chiplet integration - use cases

5. ADVANCED SEMICONDUCTOR PACKAGING FOR DIFFERENT MARKETS

  • 5.1. High-performance computing (HPC)
    • 5.1.1. Introduction to Data Center Equipment: Servers, Switches and Supervisors
    • 5.1.2. Server Board Layout (1)
    • 5.1.3. Server board Layout (2)
    • 5.1.4. Determining the Relative Numbers of Data Center Equipment
    • 5.1.5. Data Center Switch Players
    • 5.1.6. Average Switch Port Numbers
    • 5.1.7. Examples of switch architecture
    • 5.1.8. Data Center Server Unit Forecast 2022-2033 (Shipment)
    • 5.1.9. Total addressable data center CPU market forecast 2022-2033 (Shipment)
    • 5.1.10. Total addressable data center accelerator market forecast 2022-2033 (Shipment)
  • 5.2. Semiconductor packaging for CPUs in data center servers and switches
    • 5.2.1. Intel vs AMD for Server CPUs
    • 5.2.2. Advanced semiconductor packaging for Intel latest Xeon server CPU (1)
    • 5.2.3. Advanced semiconductor packaging for Intel latest Xeon server CPU (2)
    • 5.2.4. AMD chip semiconductor packaging roadmap
    • 5.2.5. Options for Integrating Multiple Chips
    • 5.2.6. AMD's semiconductor packaging choices for chiplet integration
    • 5.2.7. AMD Stacked 3D V-Cache technology for server CPU (1)
    • 5.2.8. AMD Stacked 3D V-Cache technology for server CPU (2)
    • 5.2.9. Future packaging trend for chiplet server CPU
    • 5.2.10. Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment)
  • 5.3. Semiconductor packaging for accelerators in data center servers and switches
    • 5.3.1. Accelerators in servers
    • 5.3.2. Server board layout - with accelerators (1)
    • 5.3.3. Server board layout - with accelerators (2)
  • 5.4. GPUs as data center accelerators
    • 5.4.1. Computer memory hierarchy
    • 5.4.2. HBM vs DDR for computing (1)
    • 5.4.3. Drawbacks of High Bandwidth Memory (HBM)
    • 5.4.4. Summary of HBM vs DDR
    • 5.4.5. HBM vs DDR for computing - market trend
    • 5.4.6. Approaches to package HBM and GPU
    • 5.4.7. AMD new server GPU featuring new semiconductor packaging approach
    • 5.4.8. AMD Elevated fanout bridge 2.5D
    • 5.4.9. AMD patents GPU chiplet design for future graphics cards
    • 5.4.10. AMD GPU memory choice for different applications
    • 5.4.11. NVIDIA GPU for data centers
    • 5.4.12. Computing modules with HBM (1)
    • 5.4.13. Computing modules with HBM (2)
    • 5.4.14. Intel Ponte Vecchio packaging insights
  • 5.5. FPGA as data center accelerators
    • 5.5.1. Server board layout - with FPGA accelerators
    • 5.5.2. Intel FPGA packaging
    • 5.5.3. Xilinx FPGA packaging
    • 5.5.4. High-end commercial chips based on advanced semiconductor packaging technology (1)
    • 5.5.5. High-end commercial chips based on advanced semiconductor packaging technology (2)
    • 5.5.6. Summary
    • 5.5.7. Logic-memory moving from 2D to 3D packaging
    • 5.5.8. Data center accelerator: advanced semiconductor packaging unit forecast 2022-2033 (shipment)
  • 5.6. Advanced semiconductor packaging in automotive
    • 5.6.1. Future ADAS/Autonomous driving systems: requirements, actions, and current challenges
    • 5.6.2. Three transformational pillars in automotive electronics
  • 5.7. Autonomous vehicles (AVs) - an overview
    • 5.7.1. Why Automate Cars?
    • 5.7.2. The Automation Levels in Detail
    • 5.7.3. Functions of Autonomous Driving at Different Levels
    • 5.7.4. The European Commission's Roadmap to Autonomy
    • 5.7.5. Autonomous Vehicle = Electric Vehicle?
    • 5.7.6. Typical Sensor Suite for Autonomous Cars
    • 5.7.7. What is Sensor Fusion?
    • 5.7.8. Evolution of Sensor Suite from Level 1 to Level 4
    • 5.7.9. The Coming Flood of Data in Autonomous Vehicles
    • 5.7.10. High demand for computing power in autonomous vehicles
    • 5.7.11. Semiconductor Content Increase in AVs
    • 5.7.12. Semiconductor Content Increase in EVs
    • 5.7.13. Horizon Robotics: the Chinese Embedded AI Chip Unicorn
  • 5.8. Autonomous driving platform - processors and chip packaging
    • 5.8.1. The primary differentiators for AVs will be chip design and software
    • 5.8.2. Autonomous driving platform - processors and packaging roadmap (1)
    • 5.8.3. Autonomous driving platform - processors and packaging roadmap (2)
    • 5.8.4. Chip design and packaging choice for AV computing processers from different suppliers
    • 5.8.5. NVIDIA's AV computing modules for L5 automotive
    • 5.8.6. Self-driving computing module packaging challenges
    • 5.8.7. L4+ Autonomous vehicles sales forecast 2022-2045
    • 5.8.8. Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045
    • 5.8.9. 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045
    • 5.8.10. 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045
  • 5.9. Transformation of AV chip supply chain
    • 5.9.1. VW and Ford In-House Chip Design
    • 5.9.2. Stellantis Design Chips with Foxconn
    • 5.9.3. Nvidia Autonomous Development Kit
    • 5.9.4. Nvidia - Daimler
    • 5.9.5. BMW
    • 5.9.6. Qualcomm
    • 5.9.7. Xilinx (AMD brand)
    • 5.9.8. Summary of Some Current Supply Relationships
    • 5.9.9. Future Chip Supply Summarised
    • 5.9.10. Autonomous Vertical Integration
    • 5.9.11. Expect Supply Chain to Consolidate with Increased Automation
  • 5.10. Autonomous - packaging for sensors and power modules
    • 5.10.1. Autonomous - packaging for sensors and power modules
    • 5.10.2. Packaging for sensors in ADAS (1)
    • 5.10.3. Packaging for sensors in ADAS(2)
    • 5.10.4. Radar IC Packages
  • 5.11. EV - power module packaging
    • 5.11.1. Power Module Packaging Over the Generations
  • 5.12. Package Materials & Innovations
    • 5.12.1. Traditional Power Module Packaging
    • 5.12.2. Module Packaging Material Dimensions
    • 5.12.3. Advanced Wirebonding Techniques
    • 5.12.4. Technology Evolution Beyond Al Wire Bonding
  • 5.13. Substrates
    • 5.13.1. The Choice of Ceramic Substrate Technology
    • 5.13.2. AlN: Overcoming its Mechanical Weakness
  • 5.14. Approaches to Substrate Metallisation
    • 5.14.1. Approaches to Metallisation: DPC, DBC, AMB and Thick Film Metallisation
    • 5.14.2. Direct Plated Copper (DPC): Pros and Cons
    • 5.14.3. Double Bonded Copper (DBC): Pros and Cons
    • 5.14.4. Active Metal Brazing (AMB): Pros and Cons
    • 5.14.5. Ceramics: CTE Mismatch
  • 5.15. Introduction to 5G
    • 5.15.1. Evolution of mobile communications
    • 5.15.2. Global snapshot of allocated/targeted 5G spectrum
    • 5.15.3. 5G network deployment strategy
    • 5.15.4. Two types of 5G: sub-6 GHz and mmWave
    • 5.15.5. Low, mid-band 5G is often the operator's first choice to provide 5G national coverage
    • 5.15.6. 5G commercial/pre-commercial services by frequency
  • 5.16. 5G infrastructure
    • 5.16.1. From 1G to 5G: the evolution of cellular network infrastructure
    • 5.16.2. Different RAN architectures
    • 5.16.3. Why splitting the baseband unit (BBU) is necessary in 5G
    • 5.16.4. High and Low layer split of the 5G network
    • 5.16.5. More functional splits to support diverse 5G use cases
    • 5.16.6. Evolution of Open RAN functional split
    • 5.16.7. Samsung's VRAN solution
    • 5.16.8. Ericsson's cloud RAN solution
    • 5.16.9. Open RAN deployment based on commercial off-the-shelf (COTS) hardware
    • 5.16.10. Ultra low latency networks require accelerator card
    • 5.16.11. Open RAN infrastructure arrangement
    • 5.16.12. 5G radio design trend
    • 5.16.13. Trends in 5G antennas: active antennas and massive MIMO
    • 5.16.14. Massive MIMO (mMIMO)
    • 5.16.15. Antenna array architectures for beamforming
    • 5.16.16. Software defined radio (SDR)
    • 5.16.17. Block diagram of MIMO antenna array system
    • 5.16.18. Integration of digital frontend with transceivers
    • 5.16.19. Si design for Open RAN radio (Analog Devices case)
    • 5.16.20. Marvell baseband Si for 5G Open RAN radio
    • 5.16.21. Marvell SoC for 5G networks (2)
    • 5.16.22. Xilinx's Si solution for 5G radio unit (1)
    • 5.16.23. Xilinx's Si solution for 5G radio unit (2)
    • 5.16.24. End-to-End 5G Silicon Solutions from Intel
    • 5.16.25. Intel's FPGA for 5G radio (1)
    • 5.16.26. Intel's FPGA for 5G radio (2)
    • 5.16.27. The intentions of 5G system vendors enter Si battleground (1)
    • 5.16.28. The intentions of 5G system vendors enter Si battleground (2)
    • 5.16.29. Key chipset players involved in the telecom infrastructure
    • 5.16.30. 5G base station types: macro cells and small cells
    • 5.16.31. 5G radios by MIMO size unit forecast 2022-2032 (Cumulative)
    • 5.16.32. Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative)
    • 5.16.33. Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative)
  • 5.17. 5G mmWave Antenna in Package (AiP)
    • 5.17.1. Overview of challenges, trends and innovations for mmWave 5G devices
    • 5.17.2. High frequency integration and packaging trend
    • 5.17.3. Example: Qualcomm mmWave antenna module
    • 5.17.4. High frequency integration and packaging: Requirement and Challenges
    • 5.17.5. Three ways of mmWave antenna integration
    • 5.17.6. Technology benchmark of antenna packaging technologies
    • 5.17.7. AiP development trend
    • 5.17.8. Two types of AiP structures
    • 5.17.9. Two types of IC-embedded technology
    • 5.17.10. University of Technology, Sydney: AME antennas in packages for 5G wireless devices
    • 5.17.11. Additively manufactured antenna-in-package
    • 5.17.12. Low loss materials is key for 5G mmWave AiP
    • 5.17.13. Low loss materials for AiP: Five important metrics that impact the materials selection
    • 5.17.14. Overview of low-loss materials for AiP
    • 5.17.15. Choices of low-loss materials for 5G mmWave AiP
    • 5.17.16. Key low loss materials suppliers landscape
    • 5.17.17. Benchmark of commercialised low-loss organic laminates
    • 5.17.18. Organic materials are still the mainstream choice for substrates in AiP
    • 5.17.19. Benchmark of low loss materials for AiP
    • 5.17.20. 5G AiP Summary
  • 5.18. Advanced semiconductor packaging technologies for consumer electronics
    • 5.18.1. Introduction
    • 5.18.2. TSMC's HD fanout solutions for consumer electronics
    • 5.18.3. Samsung's new galaxy smartwatch
    • 5.18.4. Packaging choices for packaging application processor environment (APE) in consumer electronics (1)
    • 5.18.5. Packaging choices for packaging application processor environment (APE) in consumer electronics (2)
    • 5.18.6. 3D packaging for APE in consumer electronics
    • 5.18.7. Future packaging trend for APE in consumer electronics
    • 5.18.8. Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033
    • 5.18.9. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1)
    • 5.18.10. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2)
    • 5.18.11. Advanced semiconductor packaging unit forecast for APE in consumer electronics remarks
    • 5.18.12. Apple's M1 ultra for workstations uses TSMC's fan-out technologies
    • 5.18.13. AMD Stacked 3D V-Cache technology for consumer desktop CPU
    • 5.18.14. Intel mobile SoC for laptops (Lakefield) advanced semiconductor packaging
    • 5.18.15. Advanced semiconductor packaging in Intel's next generation CPU Meteor Lake
    • 5.18.16. Global PC shipment forecast 2022-2033
    • 5.18.17. Advanced semiconductor packaging units in PC forecast 2022-2033 (1)
    • 5.18.18. Advanced semiconductor packaging units in PC forecast 2022-2033 (2)

6. FORECAST SUMMARY

  • 6.1. Data Center Server Unit Forecast 2022-2033 (Shipment)
  • 6.2. Total addressable data center CPU market forecast 2022-2033 (Shipment)
  • 6.3. Data center CPU: advanced semiconductor packaging unit forecast 2022-2033 (Shipment)
  • 6.4. Total addressable data center accelerator market forecast 2022-2033 (Shipment)
  • 6.5. Data center accelerator: advanced semiconductor packaging unit forecast 2022-2033 (shipment)
  • 6.6. Future ADAS/Autonomous driving systems: requirements, actions, and current challenges
  • 6.7. Three transformational pillars in automotive electronics
  • 6.8. L4+ Autonomous vehicles sales forecast 2022-2045
  • 6.9. Total addressable ADAS processor & accelerator sales market for L4+ Autonomous vehicles forecast 2022-2045
  • 6.10. 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045
  • 6.11. 3D advanced semiconductor packaging unit sales for L4+ Autonomous vehicles forecast 2022-2045
  • 6.12. Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2033
  • 6.13. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (1)
  • 6.14. Advanced semiconductor packaging unit forecast for APE (Application processor environment) in consumer electronics 2022-2033 (2)
  • 6.15. Global PC shipment forecast 2022-2033
  • 6.16. Advanced semiconductor packaging units in PC forecast 2022-2033 (1)
  • 6.17. Advanced semiconductor packaging units in PC forecast 2022-2033 (2)
  • 6.18. 5G radios by MIMO size unit forecast 2022-2032 (Cumulative)
  • 6.19. Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative)
  • 6.20. Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative)
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