3-D TSV : 중요 과제에 대한 고찰과 시장 분석

3-D TSV 기술 및 시장에 대해 조사 분석하고, 3-D TSV 기술의 메리트와 과제, 비용 구조, 주요 가공 기술과 기술 개발 동향, 주요 기업 프로파일, TSV 기기 및 재료 시장의 성장 예측 등을 정리하여 전해드립니다.

제1장 서론

제2장 중요 과제에 대한 고찰
• 3-D TSV의 추진 요인
• TSV에 의한 3-D IC의 메리트
• 비용 효율이 높은 3-D 다이 스태킹(Die Stacking) 기술의 요건
• TSV 기술의 과제
• TSV 공급망의 과제
• 3-D 패키징 기술의 제약
  • 열관리
  • 비용
  • 복잡한 설계
  • 딜리버리까지의 시간

제3장 비용 구조
• D2W·W2W 3-D 칩 스택의 비용 구조
• 소유 비용

제4장 중요 가공 기술
• 서론
• Cu 도금
• 리소그래피
  • 광 리소그래피(Optical Lithography)
  • 임프린트 리소그래피(Imprint Lithography)
  • 레지스트 도포(Resist Coat)
• 플라즈마 에칭 기술
• 스트리핑/클리닝
• 박형 웨이퍼 본딩
• 웨이퍼 박화/CMP
• 스태킹

제5장 중요 개발 구분에 대한 평가
• 서론
• Via-first : FEOL 전
  • 기기 요건
  • 재료 요건
• Via-first : FEOL 후
  • 기기 요건
  • 재료 요건
• Via-Middle
  • 기기 요건
  • 재료 요건
• Via-Last : 본딩 전
  • 기기 요건
  • 재료 요건
• Via-Last : 본딩 후
  • 기기 요건
  • 재료 요건

제6장 관련 기업 프로파일
• 칩 제조업자/패키징/서비스
• 기기 공급업체
• 재료 공급업체

제7장 시장 분석
• TSV 디바이스의 로드맵
• TSV 기기 예측
• 장비 예측
• 재료 예측

도표

Through-Silicon Via (TSV) is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction. TSV provides the high-bandwidth interconnection between stacked chips. The different TSV processes, which are more complex than initially anticipated, are analyzed.

This report analyzes the market for TSV ICs by units and wafers, and for equipment and materials used in their manufacture.

Table of Contents

Chapter 1 Introduction

Chapter 2 Insight Into Critical Issues

• 2.1 Driving Forces In 3-D TSV
• 2.2 Benefits of 3-D ICs With TSVs
• 2.3 Requirements For A Cost Effective 3-D Die Stacking Technology
• 2.4 TSV Technology Challenges
• 2.5 TSV Supply Chain Challenge
• 2.6 Limitations of 3-D Packaging Technology
  • 2.6.1 Thermal Management
  • 2.6.2 Cost
  • 2.6.3 Design Complexity
  • 2.6.4 Time to Delivery

Chapter 3 Cost Structure

• 3.1 Cost Structure of 3-D chip Stacks
• 3.2 Cost of Ownership

Chapter 4 Critical Processing Technologies

• 4.1 Introduction
• 4.2 Cu Plating
• 4.3 Lithography
  • 4.3.1 Optical Lithography
  • 4.3.2 Imprint Lithography
  • 4.3.3 Resist Coat
• 4.4 Plasma Etch Technology
• 4.5 Stripping/Cleaning
• 4.6 Thin Wafer Bonding
• 4.7 Wafer Thinning/CMP
• 4.8 Stacking
• 4.9 Metrology/Inspection

Chapter 5 Evaluation Of Critical Development Segments

• 5.1 Introduction
• 5.2 Via-first
  • 5.2.1 Equipment Requirements
  • 5.2.2 Material Requirements
• 5.3 Via-Middle
  • 5.3.1 Equipment Requirements
  • 5.3.2 Material Requirements
• 5.4 Via-Last
  • 5.4.1 Equipment Requirements
  • 5.4.2 Material Requirements
• 5.5 Interposers

Chapter 6 Profiles Of Participants

• 6.1 Chip Manufacturers/Packaging Houses/Services
• 6.2 Equipment Suppliers
• 6.3 Material Suppliers
• 6.4 R&D

Chapter 7 Market Analysis

• 7.1 TSV Device Roadmap
• 7.2 TSV Device Forecast
• 7.3 Equipment Forecast
• 7.4 Material Forecast

LIST OF TABLES

• 1.1 3-D Mass Memory Volume Comparison Between Other Technologies And TI's 3-D Technology
• 1.2 3-D Mass Memory Weight Comparison Between Other Technologies And TI's 3-D Technology
• 3.1 Cost Of Ownership Comparison
• 4.1 Via Middle Metrology/Inspection Requirements
• 4.2 Via Last Metrology/Inspection Requirements
• 7.1 Forecast Of TSV Devices By Units
• 7.2 Forecast Of TSV Devices By Wafers
• 7.3 Forecast Of TSV Equipment by Type

LIST OF FIGURES

• 1.1 3-D Technology On Dram Density
• 1.2 3-D Through-Silicon Via (TSV)
• 1.3 Graphical Illustration Of The Silicon Efficiency Between MCMs And 3-D Technology
• 1.4 Silicon Efficiency Comparison Between 3D Packaging Technology and Other Conventional Packaging Technologies
• 2.1 TSV Fabrication Process Challenges
• 2.2 TSV Fabrication Process Challenge - Cu Protrusion
• 2.3 TSV Reliability Challenges
• 2.4 Via Middle Process Integration Challenges
• 2.5 Via Middle Process Integration Challenges
• 3.1 Cost Structure of D2W and W2W
• 3.2 Assembly Cost Analysis
• 3.2 Cost Structure Of Different Vias And Tools
• 3.3 Cost Of Ownership For 5 X 50 TSV VIA Middle
• 3.4 Cost Of CMP For TSV VIA Middle Process
• 3.5 Cost Of Ownership For 10 X 100 TSV Via Middle
• 3.6 Cost Structure Of TSVs 5 X 50 µm
• 3.7 Interposer TSV: Upscaling To 10 X 100 µm
• 3.8 TSV Downscaling To 3×50 µm
• 3.9 Cost Structure Of Different Vias And Tools
• 3.10 Via First Cost Of Ownership
• 3.11 Via First Cost Of Ownership Front And Back Side
• 3.12 Via First Process Flow
• 3.13 iTSV Versus pTSV Cost Of Ownership
• 3.14 Effect Of TSV Depth And Diameter On Cost
• 4.1 Illustration Of Bosch Process
• 4.2 Key Via Middle TSV Process Steps
• 4.3 Key Last TSC Process Steps
• 5.1 VIA First, Middle, And Last Process Flows
• 5,2 VIA First TSV Process Flow
• 5.3 VIA Middle TSV Process Flow
• 5.4 Soft Reveal Process
• 5.5 VIA Last TSV Process Flow
• 5.6 Comparison Between 2.5D And 3D
• 5.7 TSV Interposer Cross Sectional Schematic With RDL Layer
• 5.8 Process Flow For RDL And UBM
• 7.1 Leading Edge TSV Roadmap
• 7.2 Forecast Of TSV Devices By Units
• 7.3 Forecast Of TSV Devices By Wafers
• 7.4 Forecast Of TSV Equipment by Type
• 7.5 Forecast Of TSV Materials