공동 패키징 메모리 : 시장 점유율 분석, 업계 동향 및 통계, 성장 예측(2026-2031년)

According to Mordor Intelligence, the co-packaged memory market size is projected to be USD 0.42 billion in 2025, USD 0.56 billion in 2026, and reach USD 1.77 billion by 2031, growing at a CAGR of 25.88% from 2026 to 2031.

This report is Segmented by Memory Type (HBM, On-Package DRAM, and More), Packaging Architecture (2. 5D Interposer-Based Packaging, Embedded Bridge-Based Packaging, and More), Application (Cloud and Enterprise Servers, and More), Customer Type (Semiconductor and AI Chip Vendors, Hyperscalers and Cloud Service Providers, and More), and Geography. The Market Forecasts are Provided in Terms of Value (USD).

Global Co-Packaged Memory Market Trends and Insights

AI Server Memory Density Requirements

AI training and inference systems no longer scale mainly through raw compute, because memory bandwidth now limits how effectively accelerator cores can stay utilized across large model workloads. NVIDIA's Blackwell architecture carries 192 GB of HBM3e and delivers 8 TB/s of memory bandwidth, which shows how close memory and compute must sit in current high-end server designs. Samsung stated in 2026 that its commercial HBM4 can deliver up to 3.3 TB/s per stack and improve power efficiency by 40% versus HBM3E, which supports the move toward denser memory attached directly to compute logic. That shift matters because each new accelerator generation consumes more HBM capacity per chip, which turns every server refresh into a larger memory event rather than a simple processor upgrade. As a result, the co-packaged memory market is expanding not only because AI server volumes are rising, but also because each installed unit now carries a much heavier memory content load than earlier platforms. This keeps demand firm even when buyers become selective on broader server spending, since memory proximity now affects model throughput, latency, and power draw at the system level.

Shift Toward HBM-Centric Package Architectures

HBM-centered packaging has moved from a premium design choice into the default layout for the highest-bandwidth AI platforms, because conventional board-level memory cannot deliver comparable throughput without far larger power and signal penalties. NVIDIA product disclosures and package-level technical documentation show that multi-stack HBM designs already provide bandwidth far above conventional DDR-based approaches, which explains why HBM now dominates the co-packaged memory market by memory technology. The co-packaged memory market also benefits from the fact that packaging standards and process flows are still evolving in ways that protect near-term manufacturability, not just peak performance. Samsung noted that HBM4 entered commercial production in 2026 with meaningful performance gains over HBM3E, which indicates that suppliers are still extracting major value from current stack designs before the next bonding transition becomes unavoidable. That matters for buyers because it allows near-term platform growth to stay anchored in proven HBM integration paths while keeping the next step toward more complex bonding methods tied to later generations. It also reinforces why the co-packaged memory market is seeing demand concentrate around suppliers that can align memory, packaging, and accelerator roadmaps without forcing abrupt design changes on customers.

High Yield Losses in TSV and Multi-Die Integration

Yield loss remains one of the strongest checks on near-term expansion, because co-packaged memory stacks accumulate risk across thousands of vertical connections and multiple bonded dies. Research from the IMAPS Device Packaging Conference showed that a single HBM layer may require 5,000 to 10,000 TSVs, and that a 12-layer stack at a 95% per-layer success rate can fall to a total stack yield near 54%. That math matters because scrap not only removes finished output, but it also consumes silicon, assembly time, materials, and scarce packaging tools that could have gone to usable product. The challenge becomes harder as interface widths rise and stack heights move from 12 layers toward 16 layers, because more density usually brings more defect sensitivity and more process tuning. Hybrid bonding will likely improve long-term scaling, but peer-reviewed work shows that bonding pressure, surface condition, and interface quality remain central to thermal and reliability outcomes. This means the co-packaged memory market can attract strong demand and still face slower usable supply growth when yields on next-generation packages take time to stabilize.

Other drivers and restraints analyzed in the detailed report include:

1. Co-Integration of Logic and Memory in Chiplet Designs
2. Hyperscaler Preference for Lower Latency and Higher Bandwidth Stacks
3. Limited Advanced Packaging Capacity for Memory Integration

For complete list of drivers and restraints, kindly check the Table Of Contents.

Segment Analysis

HBM held 84.11% of the co-packaged memory market share in 2025, which reflects its central role in systems where bandwidth is the main performance constraint rather than simple memory capacity. The co-packaged memory market keeps leaning toward HBM because current AI accelerators demand short interconnect paths and far higher throughput than off-package DRAM can supply at comparable power efficiency. NVIDIA's Blackwell platform illustrates that point, because its HBM-rich design reaches 8 TB/s of memory bandwidth and depends on close package-level integration between compute and memory. Samsung also stated that commercial HBM4 delivers up to 3.3 TB/s per stack with 40% better power efficiency than HBM3E, which reinforces why HBM remains the default path for high-end AI infrastructure in the co-packaged memory market. The current lead is therefore not only a reflection of product availability, but it is also tied to the fact that no other memory format in the 2025 to 2026 window matches HBM's blend of bandwidth density, package proximity, and accelerator compatibility.

On-package DRAM is projected to grow at a 25.91% CAGR from 2026 to 2031, which makes it the fastest-rising memory category inside the co-packaged memory market even though it starts from a much smaller base. AMD's Versal Premium Gen 2 Memory on Package design shows why, because it integrates up to 32 GB of LPDDR5X memory on package, delivers 288 GB/s bandwidth, and uses 60% less board area for customers that need a longer product life and a different cost profile than HBM. This opens room in the co-packaged memory industry for deployments in adaptive compute, edge AI, automotive, and long-lifecycle embedded systems where HBM supply, refresh cadence, and cost remain harder to justify. Emerging memory technologies still sit earlier in the adoption curve, because packaging ecosystems, interoperability, and process flows are not yet aligned to absorb them at volume across mainstream accelerator programs. UCIe 3.0 provides an important technical anchor by increasing die-to-die data rates and adding runtime power controls, which helps define how future memory forms may plug into package-level designs. The result is a two-track co-packaged memory market where HBM remains the clear revenue engine while on-package DRAM broadens the addressable base without displacing HBM at the top end.

2.5D interposer-based packaging accounted for 70.34% share of the co-packaged memory market size in 2025, which shows that the leading commercial path still favors a layout that places compute dies and multiple memory stacks on a shared interposer. The co-packaged memory market benefits from this architecture because it balances very high bandwidth with a manufacturing base that is more mature than full 3D alternatives in current production programs. Interposer-based designs also fit the way most present accelerator platforms are qualified, since they allow dense memory placement without yet forcing the most demanding thermal and bonding conditions seen in deeper vertical stacks. That is why competing approaches such as embedded bridge and fan-out or RDL packaging remain more relevant in networking, telecom, and cost-sensitive compute applications than in the top tier of AI training infrastructure. The present dominance of 2.5D is therefore closely tied to practical manufacturability, packaging line availability, and customer comfort with known process windows across the co-packaged memory market.

3D stacked packaging is projected to expand at a 26.13% CAGR from 2026 to 2031, because it offers a path to even tighter integration when hybrid bonding, thermal control, and yield management improve enough for broader use. Research presented at IEEE ECTC 2025 showed that TSMC's SoIC Cool-Stacking approach reduced thermal resistance by 77% versus micro-bump schemes, which points to a stronger long-term case for high-density 3D package designs. At the same time, imec showed in late 2025 that a 3D HBM-on-GPU layout can drive far higher peak temperatures than a comparable 2.5D package unless system and technology co-optimization is applied, which explains why adoption still depends on cooling and design refinement rather than on package density alone. This means the co-packaged memory market will likely move into 3D in stages, with the earliest traction centered on applications that can justify the engineering effort, thermal management cost, and slower yield ramp. Equipment lead times and learning curves for hybrid bonding also keep 2.5D firmly in front for now, even as 3D stacked formats set the growth pace. The co-packaged memory market, therefore, shows a split between today's dominant production standard and tomorrow's most aggressive performance path.

Complete Report Scope:

• By Memory Type
  • High-Bandwidth Memory (HBM)
  • On-Package DRAM
  • Emerging Memory Technologies
• By Packaging Architecture
  • 2.5D Interposer-Based Packaging
  • Embedded Bridge-Based Packaging
  • Fan-Out / RDL-Based Packaging
  • 3D Stacked Packaging
• By Application
  • AI Accelerators
  • High-Performance Computing and Supercomputing
  • Cloud and Enterprise Servers
  • Data Center Networking and Telecom Infrastructure
  • Automotive and Edge Compute Platforms
• By Customer Type
  • Semiconductor and AI Chip Vendors
  • Hyperscalers and Cloud Service Providers
  • Server, Storage, and Networking OEMs
  • Automotive and Industrial Electronics Companies
• By Geography
  • North America
    • United States
    • Canada
    • Mexico
  • Europe
    • Germany
    • United Kingdom
    • France
    • Italy
    • Rest of Europe
  • Asia-Pacific
    • China
    • Japan
    • South Korea
    • India
    • Southeast Asia
    • Rest of Asia-Pacific
  • South America
  • Middle East and Africa

Geography Analysis

Asia-Pacific held 56.58% of the co-packaged memory market share in 2025 and is projected to record the fastest CAGR at 26.27% through 2031, which reflects the region's deep concentration in HBM production, foundry capability, and advanced package assembly. The co-packaged memory market remains heavily anchored in South Korea and Taiwan because Samsung Electronics and SK Hynix lead memory supply, while Taiwan stays central to interposer-led packaging and outsourced semiconductor assembly. This regional structure matters because it brings design execution, memory fabrication, and package-level integration into close physical proximity, which shortens iteration cycles for high-bandwidth AI platforms. China is evolving in a different way, with JCET planning a CNY 7.8 billion (USD 1.15 billion) advanced packaging facility in Shanghai Lingang to serve computing and automotive electronics customers as local packaging ambition rises. The co-packaged memory market, therefore, draws much of its scale from Asia-Pacific not only because factories are located there, but also because the region has the most complete operating chain for HBM-linked packaging today.

North America represents a smaller production base in the co-packaged memory market, yet it holds rising strategic weight because many hyperscalers, AI chip designers, and advanced packaging policy programs are concentrated there. NIST stated in January 2025 that the U.S. Department of Commerce finalized USD 1.4 billion in NAPMP awards, including support for the Advanced Packaging Piloting Facility in Arizona and several substrate and fan-out processing programs. Amkor's investor materials showed that its Arizona advanced packaging campus remained on track for tool installation in 2027 and production start in 2028, which gives North America a clearer route toward domestic 2.5D packaging and HBM integration capacity. That means the region's role in the co-packaged memory market is still stronger on demand, design, and policy than on immediate supply, but the effort to change that balance is now clearly underway.

Europe remains smaller in direct production terms, though it carries strategic value through process research and package-level thermal work that can influence later commercial adoption. imec's published 2025 work on 3D HBM-on-GPU thermal mitigation shows why Europe matters to the co-packaged memory market even without equivalent scale in HBM manufacturing capacity. Japan, while counted within Asia-Pacific, has become more notable through Micron's HBM-related ramp activity, which adds another production node to the broader regional supply base. Middle East and Africa remain early in adoption and largely demand-led, while South America has no meaningful production presence in the current forecast window. This leaves the co-packaged memory market geographically concentrated, with diversification efforts growing but not yet strong enough to alter the center of gravity away from Asia-Pacific.

1. Samsung Electronics Co., Ltd.
2. SK hynix Inc.
3. Micron Technology, Inc.
4. Taiwan Semiconductor Manufacturing Company Limited
5. Intel Corporation
6. Advanced Micro Devices, Inc.
7. NVIDIA Corporation
8. Amkor Technology, Inc.
9. ASE Technology Holding Co., Ltd.
10. JCET Group Co., Ltd.
11. Powertech Technology Inc.
12. Siliconware Precision Industries Co., Ltd.
13. Kioxia Corporation
14. Nanya Technology Corporation
15. Renesas Electronics Corporation
16. Hanmi Semiconductor Co., Ltd.
17. Marvell Technology, Inc.
18. Broadcom Inc.
19. Rambus Inc.
20. Applied Materials, Inc.

Additional Benefits:

• The market estimate (ME) sheet in Excel format
• 3 months of analyst support

TABLE OF CONTENTS

1 INTRODUCTION

• 1.1 Study Assumptions and Market Definition
• 1.2 Scope of the Study

2 RESEARCH METHODOLOGY

3 EXECUTIVE SUMMARY

4 MARKET LANDSCAPE

• 4.1 Market Overview
• 4.2 Market Drivers
  • 4.2.1 AI Server Memory Density Requirements
  • 4.2.2 Shift Toward HBM-Centric Package Architectures
  • 4.2.3 Co-Integration of Logic and Memory in Chiplet Designs
  • 4.2.4 Hyperscaler Preference for Lower Latency and Higher Bandwidth Stacks
  • 4.2.5 Government Subsidies for Advanced Packaging Ecosystems
  • 4.2.6 Memory-Adjacent Power Efficiency Gains in Accelerated Computing
• 4.3 Market Restraints
  • 4.3.1 High Yield Losses in TSV and Multi-Die Integration
  • 4.3.2 Limited Advanced Packaging Capacity for Memory Integration
  • 4.3.3 Thermal Dissipation and Reliability Constraints
  • 4.3.4 High Capital Intensity and Qualification Cycles
• 4.4 Supply Chain Analysis
• 4.5 Regulatory Landscape
• 4.6 Technological Outlook
• 4.7 Porter's Five Forces Analysis
  • 4.7.1 Bargaining Power of Suppliers
  • 4.7.2 Bargaining Power of Buyers
  • 4.7.3 Threat of New Entrants
  • 4.7.4 Threat of Substitutes
  • 4.7.5 Competitive Rivalry

5 MARKET SIZE AND GROWTH FORECASTS (VALUE)

• 5.1 By Memory Type
  • 5.1.1 High-Bandwidth Memory (HBM)
  • 5.1.2 On-Package DRAM
  • 5.1.3 Emerging Memory Technologies
• 5.2 By Packaging Architecture
  • 5.2.1 2.5D Interposer-Based Packaging
  • 5.2.2 Embedded Bridge-Based Packaging
  • 5.2.3 Fan-Out / RDL-Based Packaging
  • 5.2.4 3D Stacked Packaging
• 5.3 By Application
  • 5.3.1 AI Accelerators
  • 5.3.2 High-Performance Computing and Supercomputing
  • 5.3.3 Cloud and Enterprise Servers
  • 5.3.4 Data Center Networking and Telecom Infrastructure
  • 5.3.5 Automotive and Edge Compute Platforms
• 5.4 By Customer Type
  • 5.4.1 Semiconductor and AI Chip Vendors
  • 5.4.2 Hyperscalers and Cloud Service Providers
  • 5.4.3 Server, Storage, and Networking OEMs
  • 5.4.4 Automotive and Industrial Electronics Companies
• 5.5 By Geography
  • 5.5.1 North America
    • 5.5.1.1 United States
    • 5.5.1.2 Canada
    • 5.5.1.3 Mexico
  • 5.5.2 Europe
    • 5.5.2.1 Germany
    • 5.5.2.2 United Kingdom
    • 5.5.2.3 France
    • 5.5.2.4 Italy
    • 5.5.2.5 Rest of Europe
  • 5.5.3 Asia-Pacific
    • 5.5.3.1 China
    • 5.5.3.2 Japan
    • 5.5.3.3 South Korea
    • 5.5.3.4 India
    • 5.5.3.5 Southeast Asia
    • 5.5.3.6 Rest of Asia-Pacific
  • 5.5.4 South America
  • 5.5.5 Middle East and Africa

6 COMPETITIVE LANDSCAPE

• 6.1 Market Concentration
• 6.2 Strategic Moves
• 6.3 Market Positioning Analysis
• 6.4 Company Profiles (includes Global Level Overview, Market Level Overview, Core Segments, Financials as available, Strategic Information, Market Rank/Share, Products and Services, Recent Developments)
  • 6.4.1 Samsung Electronics Co., Ltd.
  • 6.4.2 SK hynix Inc.
  • 6.4.3 Micron Technology, Inc.
  • 6.4.4 Taiwan Semiconductor Manufacturing Company Limited
  • 6.4.5 Intel Corporation
  • 6.4.6 Advanced Micro Devices, Inc.
  • 6.4.7 NVIDIA Corporation
  • 6.4.8 Amkor Technology, Inc.
  • 6.4.9 ASE Technology Holding Co., Ltd.
  • 6.4.10 JCET Group Co., Ltd.
  • 6.4.11 Powertech Technology Inc.
  • 6.4.12 Siliconware Precision Industries Co., Ltd.
  • 6.4.13 Kioxia Corporation
  • 6.4.14 Nanya Technology Corporation
  • 6.4.15 Renesas Electronics Corporation
  • 6.4.16 Hanmi Semiconductor Co., Ltd.
  • 6.4.17 Marvell Technology, Inc.
  • 6.4.18 Broadcom Inc.
  • 6.4.19 Rambus Inc.
  • 6.4.20 Applied Materials, Inc.

7 MARKET OPPORTUNITIES AND FUTURE OUTLOOK

• 7.1 White-Space and Unmet-Need Assessment