생성형 AI 하드웨어 재료 시장(2027-2037년)

The generative AI hardware materials market covers the materials and components used to build AI training and inference systems, from raw substrates and gases through to finished server racks. Demand is driven by hyperscaler, enterprise and sovereign capital expenditure on AI datacentres, and by the growing share of AI compute performed at the edge.

System performance is limited by a set of physical constraints rather than by model design. Compute throughput is limited by reticle area and transistor density. Memory bandwidth is limited by HBM stack height and pin width. Interconnect bandwidth is limited by signal attenuation in copper traces above roughly 224 Gbps per lane. Heat removal is limited by thermal interface conductivity and coolant flow rate. Power delivery is limited by IR drop and voltage regulator efficiency. Progress against each constraint depends on a specific materials or packaging development, which is why this layer determines how quickly AI compute capacity can be added.

The market is structured in nine layers: raw materials, gases and photoresists; power semiconductors and delivery; thermal materials and cooling; photonics packaging; substrates and interposers; advanced packaging; HBM and the memory subsystem; AI accelerator silicon; and AI servers and racks. A related but separate segment is the datacentre construction supply chain, covering power infrastructure, cooling plant, buildings and engineering services.

Growth rates differ substantially by layer. AI accelerator silicon is the largest segment but grows more slowly than several of the layers below it. HBM and advanced packaging gain share over the forecast period, as stack heights increase and CoWoS-class packaging capacity remains tight. Photonics packaging and datacentre power semiconductors grow fastest from a smaller base, as co-packaged optics moves into volume production and rack power levels rise above 300 kW. Cooling shifts away from air: direct liquid cooling and immersion account for more than 60% of new AI deployments by 2030.

Two structural characteristics are relevant to suppliers and buyers. The first is geographic concentration. Taiwan, South Korea and Japan account for most leading-edge silicon, memory, packaging, substrate and specialty materials capacity, and CoWoS-class packaging is the most constrained single step. The second is the effect of export controls, which have led to a separate hardware supply chain in China with its own suppliers and process node limits. The capability gap between the two is narrowing fastest in small-model inference and slowest in frontier model training.

Report contents include:

• Executive summary - headline findings, the hardware bottleneck, value-chain map and implications by stakeholder
• The compute stack - training and inference economics, cloud, edge and sovereign AI, and the cost weighting of memory and packaging
• AI accelerator silicon - GPUs, hyperscaler ASICs, alternative architectures, the Chinese ecosystem, foundry roadmaps and wafer-level integration
• AI-driven chip design (EDA) - incumbent vendor initiatives, the startup cohort and AI-EDA market forecasts
• High bandwidth memory and beyond - HBM roadmap and capacity, custom HBM, compute-in-memory, CXL pooling and 3D DRAM
• Advanced packaging and substrates - 2.5D and 3D integration, CoWoS capacity, ABF and FC-BGA substrates, interposers, hybrid bonding and OSAT capacity
• Co-packaged optics and silicon photonics - CPO architecture, optical I/O chiplets, photonics foundries and packaging supply chain
• Thermal management - thermal interface materials, vapour chambers, cold plates, immersion and microfluidic cooling
• Power delivery and the GaN/SiC transition - 48V and 800V HVDC architectures, SiC and GaN device and substrate supply, VRMs, server PSUs and backside power delivery
• Networking and optical materials - switch silicon, pluggable transceivers, DSP and SerDes, III-V materials, NICs, DPUs and connectors
• Datacentre construction - power infrastructure including SMRs, facility cooling, modular designs and site selection
• Edge GenAI hardware - AI smartphones and PCs, automotive silicon, robotics compute and edge accelerator start-ups
• Regional analysis - Taiwan, South Korea, Japan, China, Southeast Asia, the United States, Europe and Israel
• Supply chain and geopolitics - China's domestic supply chain, CHIPS Act implementation, critical materials and single-point-of-failure analysis
• Sustainability and embodied carbon - operational emissions, fab embodied carbon, water use, renewable procurement and disclosure standards
• Market forecasts and strategic outlook - segment, regional and customer-tier forecasts, choke-point analysis, M&A and investment framework
• Appendix - methodology, definitions, abbreviations, sources and year-by-year forecast outputs

Companies profiled include 1X Technologies, 3M, Acbel Polytech, Accelink Technologies, Achronix Semiconductor, Advanced Micro Devices (AMD), AGC (Asahi Glass), Agility Robotics, AheadComputing, Ajinomoto FineTechno (ABF), Akhan Semiconductor, Alibaba THead (PingTouGe), Alpha Assembly Solutions (MacDermid Alpha), Alphabet Inc. (Google), Amazon Web Services (AWS), Ambarella, Amber Semiconductor (AmberSemi), AMD, Amkor Technology, Amphenol Corporation, Anduril Industries, Apple Inc., Applied Materials, Apptronik, Arago, ASE Group, ASE Technology Holding (incl. SPIL), Asetek, Asia Vital Components (AVC), ASMPT, Asperitas, Astera Labs, Astrus, AT&S (Austria Technologie & Systemtechnik), Auras Technology, Avalanche Technology, Axelera AI, Axera Technology, AXT Inc., Ayar Labs, BE Semiconductor Industries (BESI), Biren Technology, Black Sesame Technologies, Blaize, Broadcom Inc., Cambricon Technologies, Cambridge GaN Devices (CGD), Carbice Corporation, Celero Communications, Cerebras Systems, Chemours Company, ChipAgents, Chipmind, ChipMOS Technologies, Chiral, Ciena, Cisco Systems, Claros, Coherent Corp., ColorChip, Cooler Master Co., CoolIT Systems, CoreWeave Inc., Corintis, Corning Incorporated, Crossbar Inc., Crusoe Energy Systems, CXMT (ChangXin Memory Technologies), DEEPX, Delta Electronics, d-Matrix, DOW Inc., Dust Photonics, Eaton Corporation, EdgeCortix, EFFECT Photonics, Efficient Computer, Efficient Power Conversion (EPC), Element Six (e6), Eliyan, Empower Semiconductor, Engineered Fluids, Eoptolink Technology, Eridu, Etched.ai, Ethernovia, EuQlid, EV Group (EVG), Everspin Technologies, Fabric8Labs, Fabrinet, Femtum, Ferroelectric Memory Company (FMC), Figure AI, Fourier Intelligence, Foxconn Industrial Internet (FII), Foxconn Interconnect Technology (FIT), Frore Systems, FSP Group, Fujipoly, Furiosa AI, G42, Gaianixx, Galatek, Gigalight, Google, Great Sky, Green Revolution Cooling (GRC), GreenWaves Technologies, Groq Inc., GS Microelectronics (GSME), Hailo Technologies, Henkel AG, Heraeus, Hesheng Silicon Industry, Hisense Broadband, HiSilicon (Huawei), Hitachi Energy, Hon Hai (Foxconn), Honeywell International, Horizon Robotics, Hua Tian Technology (HT-Tech), Huawei Technologies, Huawei Technologies (HiSilicon), Hummink, Ibiden Co. Ltd., Iceotope Technologies, Iluvatar CoreX, Indium Corporation, Infineon Technologies AG, Innolight Technology, Innoscience Technology, Intel, Intel Corporation, Intel Foundry, IQE plc, JCET Group, JetCool Technologies, Kandou AI, Kaneka Corporation, Kinsus Interconnect Technology, Kioxia Holdings, Kneron, Kulicke & Soffa Industries (K&S), Kyocera Corporation and more.....

1 EXECUTIVE SUMMARY

• 1.1 Key Findings
• 1.2 The Generative AI Hardware Bottleneck
• 1.3 Materials Value Chain at a Glance
• 1.4 Eleven-Year Forecast Highlights
• 1.5 Strategic Implications for Asian Foundries, OSAT, Memory, Substrate, and Cooling Vendors
• 1.6 Differentiation vs. Adjacent Coverage
• 1.7 Major Market Players

2 THE COMPUTE STACK BEHING GENERATIVE

• 2.1 Training vs. Inference Economics
  • 2.1.1 Pre-training, post-training, RLHF compute splits
  • 2.1.2 Inference token economics and serving infrastructure
  • 2.1.3 Test-time compute and reasoning-model demand
• 2.2 Cloud, Edge, and Sovereign AI
  • 2.2.1 Hyperscaler clusters at 100,000-GPU scale
  • 2.2.2 Enterprise on-prem and neocloud deployments
  • 2.2.3 Sovereign AI build-outs
  • 2.2.4 Edge inference cross-reference
• 2.3 Why Memory Bandwidth and Packaging Dominate Cost
  • 2.3.1 The memory wall in LLM serving
  • 2.3.2 HBM ASP as percentage of AI accelerator BOM
  • 2.3.3 CoWoS as the constraining bottleneck
• 2.4 Materials and Components as the New Bottleneck
• 2.5 Hyperscaler vs. Enterprise vs. Sovereign Capex
• 2.6 Company Profiles 43 (9 company profiles)

3 AI ACCELERTOR SILICON

• 3.1 GPUs
  • 3.1.1 NVIDIA roadmap: Hopper → Blackwell → Blackwell Ultra → Rubin → Rubin Ultra
  • 3.1.2 NVL72 rack architecture and post-Rubin scale-up
  • 3.1.3 AMD MI300X → MI355X → MI400 trajectory
  • 3.1.4 Intel Gaudi and the post-Gaudi roadmap
• 3.2 Custom Hyperscaler ASICs
  • 3.2.1 Google TPU v5/v6/v7 and ML supercomputer architecture
  • 3.2.2 AWS Trainium 2/3 and Inferentia
  • 3.2.3 Microsoft Maia and Cobalt
  • 3.2.4 Meta MTIA generations
  • 3.2.5 ASIC NRE economics and break-even analysis
• 3.3 Domain-Specific and Challenger Architectures
  • 3.3.1 Cerebras WSE-3 wafer-scale
  • 3.3.2 Groq LPU deterministic inference
  • 3.3.3 SambaNova RDU and dataflow
  • 3.3.4 Tenstorrent, d-Matrix, Etched, Rivos, Lightmatter
• 3.4 Chinese AI Chip Ecosystem
  • 3.4.1 Huawei Ascend 910C / 910D / 950
  • 3.4.2 Cambricon, Biren, Moore Threads, Iluvatar CoreX
  • 3.4.3 Alibaba T-Head Hanguang and PingTouGe
  • 3.4.4 Domestic substitution timeline to gen-on-gen parity
• 3.5 Process Nodes and Foundry Roadmaps
  • 3.5.1 TSMC: N3 → N3P → N2 → N2P → A16 → A14
  • 3.5.2 Samsung Foundry: 3GAP → 2GAP → SF1.4
  • 3.5.3 Intel Foundry: 18A → 14A and external customer pipeline
  • 3.5.4 SMIC: N+1 / N+2 and the EUV-free 5nm question
  • 3.5.5 EUV and High-NA EUV adoption curves
• 3.6 Wafer-Level Integration and Reticle Stitching
• 3.7 Company Profiles 70 (53 company profiles)

4 AI-DRIVEN CHIP DESIGN (EDA)

• 4.1 The EDA Bottleneck in the AI Hardware Era
• 4.2 The Recursive Loop: AI Designing AI Hardware
• 4.3 The Incumbent EDA Vendors' AI Initiatives
• 4.4 The Startup Cohort: Four Distinct Approaches
  • 4.4.1 Agentic AI for digital design and verification
  • 4.4.2 Physics-AI for simulation and advanced packaging
  • 4.4.3 AI for analog and PCB design
  • 4.4.4 EDA-adjacent silicon and applied AI
• 4.5 Geographic Distribution
• 4.6 Market Forecast: AI-EDA Tools 2026-2037
• 4.7 Strategic Implications
• 4.8 Company profiles 129 (6 company profiles)

5 HIGH BANDWIDTH MEMORY AND BEYOND

• 5.1 HBM Architecture and TSV Stacking Fundamentals
• 5.2 HBM Generation Roadmap
  • 5.2.1 HBM3 / HBM3E specifications and deployment
  • 5.2.2 HBM4 / HBM4E: pin width doubling and base-die logic
  • 5.2.3 HBM5 / HBM5E: 2031-2037 architecture directions
• 5.3 Memory Makers and Capacity Outlook
  • 5.3.1 SK hynix strategy, products, capex through 2030
  • 5.3.2 Samsung HBM3E re-qualification and HBM4 catch-up
  • 5.3.3 Micron HBM3E entry and AI customer share gains
  • 5.3.4 HBM bit-shipment and wafer-capacity forecasts
• 5.4 Custom HBM (cHBM) and Base-Die Innovation
  • 5.4.1 Customer-specific HBM with NVIDIA, Broadcom, Google
  • 5.4.2 Standard vs custom HBM revenue split through 2030
• 5.5 Compute-in-Memory and Processing-in-Memory at Scale
• 5.6 Emerging Memory for AI Datacenters
  • 5.6.1 Storage-class memory after 3D XPoint
• 5.7 Memory Pooling and CXL Fabrics
• 5.8 3D DRAM - The Post-2030 Path
• 5.9 Company Profiles 153 (23 company profiles)

6 ADVANCED PACKAGING AND SUBSTRATE MATERIALS

• 6.1 The 2.5D / 3D Architecture Continuum
• 6.2 TSMC CoWoS and the Capacity Constraint
  • 6.2.1 CoWoS-S, CoWoS-L, CoWoS-R roadmap
  • 6.2.2 CoWoS-Photonics and CoWoP
  • 6.2.3 CoWoS capacity expansion: 2024 vs. 2026 vs. 2028 vs. 2030
  • 6.2.4 SoIC, SoIC-X, SoIC-P: Hybrid-Bonded Stacks
• 6.3 Intel and Samsung Advanced Packaging
  • 6.3.1 Intel: EMIB, EMIB-T, Foveros, Foveros Direct, Foveros Omni
  • 6.3.2 Samsung: I-Cube, X-Cube, H-Cube
• 6.4 Substrate Technologies (ABF, FC-BGA)
  • 6.4.1 ABF supply oligopoly
  • 6.4.2 Glass core substrate (Intel, ASE, SCHOTT)
• 6.5 Interposer Materials (Silicon TSV, Glass, Organic RDL)
• 6.6 Hybrid Bonding and Copper-to-Copper Interconnect
  • 6.6.1 Hybrid bonding equipment ecosystem
  • 6.6.2 HBM4 adoption of hybrid bonding
• 6.7 OSAT Capacity and Asian Dominance
• 6.8 Advanced Packaging Materials Suppliers
• 6.9 Company Profiles 188 (56 company profiles)

7 CO-PACKAGED OPTICS AND SILICON PHOTONICS FOR AI

• 7.1 The Optical Interconnect Imperative
• 7.2 CPO Architecture and the Two Network Layers
• 7.3 TSMC COUPE, CoWoS-Photonics, iOIS
  • 7.3.1 TSMC photonics design ecosystem
  • 7.3.2 CoWoP and the NVIDIA Rubin transition
• 7.4 ASE VIPack and the Merchant Photonics Packaging Layer
• 7.5 Optical I/O Chiplets: AyarLabs, Lightmatter, Celestial AI
  • 7.5.1 AyarLabs TeraPHY
  • 7.5.2 Lightmatter Passage
  • 7.5.3 Celestial AI Photonic Fabric and the Marvell acquisition
• 7.6 Switch Silicon and Co-Packaged Optical Engines
• 7.7 Silicon Photonics Foundries
• 7.8 Photonics Packaging Materials and Supply Chain
• 7.9 Market Sizing for Photonics Packaging 2026-2037
• 7.10 Company Profiles 253 (28 company profiles)

8 THERMAL MANAGEMENT FOR AI DATA CENTERS

• 8.1 The Thermal Crisis: Power Density at the Package Level
• 8.2 Thermal Interface Materials (TIMs)
  • 8.2.1 Liquid metal TIM and the gallium corrosion problem
  • 8.2.2 Solder TIM (indium and SnAg)
  • 8.2.3 Diamond-based TIMs and emerging materials
• 8.3 Heat Spreaders, Vapor Chambers, and Heat Pipes
• 8.4 Cold Plates and Direct-to-Chip Liquid Cooling
  • 8.4.1 Cold plate design and microchannel geometry
  • 8.4.2 The cold plate supply chain bottleneck
• 8.5 Immersion Cooling
  • 8.5.1 Single-phase immersion: mineral oil and synthetic dielectrics
  • 8.5.2 Two-phase immersion: fluorocarbons and the PFAS challenge
• 8.6 Microfluidic and In-Package Cooling
  • 8.6.1 Microfluidic ecosystem and the first commercial applications
  • 8.6.2 Coolant Distribution Units, Manifolds, and Facility Plumbing
• 8.7 Market Forecast: AI-Tied Thermal Management 2024-2037
• 8.8 Company Profiles 292 (40 company profiles)

9 POWER DELIVERY AND GAN/SIC TRANSITION

• 9.1 The Power Crisis: From 12V to 48V to 800V HVDC
• 9.2 The Power Hierarchy: System → Board → Package → Die
  • 9.2.1 48V tray architecture and the OCP standard
  • 9.2.2 800V HVDC at the rack and the Rubin transition
• 9.3 SiC Devices and Substrate Supply
  • 9.3.1 SiC substrate supply: the bottleneck
• 9.4 GaN Devices: Lateral, Vertical, Cascode
  • 9.4.1 GaN switching speed and AI server PSU applications
  • 9.4.2 Vertical GaN: the post-2027 trajectory
• 9.5 Voltage Regulator Modules and Multi-Phase Point-of-Load
  • 9.5.1 The Monolithic Power Systems advantage in AI VRMs
  • 9.5.2 Vertical power delivery and the package-integrated VRM
• 9.6 Server Power Supply Units and Rack Rectifier Shelves
• 9.7 Backside Power Delivery (BSPDN)
  • 9.7.1 Intel PowerVia (18A)
  • 9.7.2 TSMC backside power (A16)
  • 9.7.3 Samsung BSPDN
• 9.8 Market Forecast: AI Datacenter Power Semiconductors 2024-2037
• 9.9 Company Profiles 343 (42 company profiles)

10 NETWORKING AND OPTICAL MATERIALS

• 10.1 The Three Network Layers in an AI Datacenter
• 10.2 Switch Silicon Roadmap
  • 10.2.1 Tomahawk 6 Davisson and the CPO inflection
  • 10.2.2 NVIDIA Spectrum-X and Quantum-X
  • 10.2.3 Ultra Ethernet Consortium (UEC)
• 10.3 Pluggable Optical Transceivers
  • 10.3.1 Volume optical transceiver suppliers
  • 10.3.2 Optical transceiver assembly: Fabrinet, Jabil, Luxshare
• 10.4 DSP and SerDes for Optical Transceivers
  • 10.4.1 Marvell's DSP business and the AI optical transceiver
  • 10.4.2 Linear Pluggable Optics (LPO) and the DSP-less transceiver
• 10.5 III-V Materials Layer: InP, GaAs, GaN-Photonics
• 10.6 NICs, DPUs, and SmartNICs
• 10.7 Cables, Connectors, and Direct Attach Copper
• 10.8 Market Forecast: AI-Tied Networking and Optical 2024-2037
• 10.9 Company Profiles 394 (36 company profiles)

11 DATA CENTER CONSTRUCTION AND SUSTAINABILITY

• 11.1 The AI Datacenter Buildout: Scale and Scope
• 11.2 Power Infrastructure: Grid, On-Site Generation, and SMRs
  • 11.2.1 Behind-the-meter natural-gas generation
  • 11.2.2 Nuclear restart and Small Modular Reactor procurement
  • 11.2.3 Renewable energy procurement at hyperscaler scale
  • 11.2.4 Switchgear and transformers: the silent bottleneck
• 11.3 Facility-Level Cooling Architecture
• 11.4 Construction Supply Chain and Modular Datacenter Architecture
• 11.5 Geographic Concentration and Site Selection
  • 11.5.1 The Top 12 AI Datacenter Regions (2026)
  • 11.5.2 Climate as a constraint
• 11.6 PUE, WUE, and Sustainability Metrics
  • 11.6.1 Carbon-Free Energy (CFE) accounting
  • 11.6.2 Embodied carbon and circular economy
• 11.7 Regulatory Framework
  • 11.7.1 Permit and interconnection timelines
• 11.8 Market Forecast: AI Datacenter Construction Supply Chain 2024-2037

12 EDGE GENAI HARDWARE

• 12.1 The Edge AI Taxonomy
• 12.2 AI Smartphones
  • 12.2.1 Apple Neural Engine evolution
• 12.3 AI PCs
  • 12.3.1 NVIDIA's AI PC entry
  • 12.3.2 Snapdragon X Elite and Qualcomm's PC push
• 12.4 NVIDIA Jetson and the Embedded AI Platform
  • 12.4.1 Jetson AGX Thor and humanoid robotics
• 12.5 Automotive AI Silicon
  • 12.5.1 NVIDIA DRIVE Thor and the L4 autonomous driving platform
  • 12.5.2 Tesla FSD and the captive silicon path
• 12.6 Humanoid Robotics: The Emerging Edge AI Compute Frontier
  • 12.6.1 Humanoid robot unit volumes and silicon revenue forecast
• 12.7 Edge AI Accelerator Start-ups
• 12.8 Edge AI Memory: LPDDR5X, On-Chip SRAM, eMRAM
• 12.9 Market Forecast: Edge AI Silicon 2024-2037
• 12.10 Company Profiles 450 (51 company profiles)

13 REGIONAL ANALYSIS: GEOGRAPHY OF THE GENAI HARDWARE SUPPLY CHAIN

• 13.1 The Asian Concentration
• 13.2 Taiwan
  • 13.2.1 The TSMC scale
  • 13.2.2 The Taiwan supply chain depth
  • 13.2.3 Taiwan's geographic concentration risk
• 13.3 South Korea
  • 13.3.1 SK hynix as the strategic anchor
  • 13.3.2 Samsung: vertical integration across the stack
  • 13.3.3 Korean specialty positions
• 13.4 Japan
  • 13.4.1 Kumamoto and the broader Japanese fab expansion
• 13.5 China
  • 13.5.1 Chinese domestic AI silicon volume and trajectory
  • 13.5.2 The SMIC constraint
  • 13.5.3 China's strength layers
• 13.6 Southeast Asia and India
  • 13.6.1 Malaysian AI infrastructure
  • 13.6.2 India's emerging fab and OSAT capacity
  • 13.6.3 ASEAN AI cloud and sovereign-AI initiatives
• 13.7 The United States
  • 13.7.1 The CHIPS Act build-out
  • 13.7.2 The US labour and supply chain constraints
• 13.8 Europe and Israel
  • 13.8.1 ASML
  • 13.8.2 European Chips Act and the limits of European industrial policy
  • 13.8.3 Israel's specialty position
• 13.9 The Rest of World: Niche Capabilities and Sovereign Ambitions
• 13.10 Aggregate Regional Capture: Scenario Analysis 2026-2037

14 SUPPLY CHAIN AND GEOPOLITICS

• 14.1 The Defining Tensions
• 14.2 The China Strategy: Sovereign Stack and Domestic Substitution
  • 14.2.1 SMIC's role and the EUV-free leading-edge path
  • 14.2.2 The CXMT and JHICC HBM ramp
  • 14.2.3 China's wafer-fab equipment indigenisation
• 14.3 US CHIPS Act Implementation and Domestic Reshoring
  • 14.3.1 TSMC Arizona
  • 14.3.2 Samsung Taylor
  • 14.3.3 Intel Foundry
  • 14.3.4 Micron's CHIPS-supported expansion
  • 14.3.5 The labour and ecosystem constraints
• 14.4 European Chips Act and Strategic Autonomy
  • 14.4.1 The European specialty position
• 14.5 The Critical Materials Layer
  • 14.5.1 Rare earths
  • 14.5.2 Gallium and germanium
  • 14.5.3 Neon and specialty gases
  • 14.5.4 Specialty quartz, silicon, and substrates
• 14.6 Single-Point-of-Failure Analysis
• 14.7 Scenarios for Supply Chain Resilience
  • 14.7.1 The "successful diversification" scenario (Bull case for resilience)
  • 14.7.2 The "concentrated capacity" scenario (Base case)
  • 14.7.3 The "geopolitical disruption" scenario (Bear case for resilience)
• 14.8 Sovereign AI as a Strategic Demand Driver

15 SUSTAINABILITY AND EMBODIED CARBON

• 15.1 The Sustainability Stakes
• 15.2 Operational Emissions: Training, Inference, and the Cooling Energy Tax
  • 15.2.1 Training versus inference: the dominant share
• 15.3 Embodied Carbon in Semiconductor Manufacturing
  • 15.3.1 The PFC and process-gas problem
  • 15.3.2 Embodied carbon at the device level
  • 15.3.3 Server-level and facility-level embodied carbon
• 15.4 Water, Chemicals, and Resource Intensity
  • 15.4.1 PFAS chemistry and the transition
• 15.5 Renewable Energy Procurement at Hyperscaler Scale
  • 15.5.1 Nuclear restart and SMR as carbon-free baseload
  • 15.5.2 On-site natural gas: the carbon offset
• 15.6 Heat Recovery, Circular Economy, and End-of-Life
  • 15.6.1 Heat recovery and district heating
  • 15.6.2 Circular economy and component reuse
• 15.7 Carbon Accounting Standards and Corporate Disclosure
  • 15.7.1 Scope 1, 2, 3 framework
  • 15.7.2 EU Corporate Sustainability Reporting Directive
  • 15.7.3 SEC climate disclosure rules
  • 15.7.4 Carbon pricing and offsets
• 15.8 Green Manufacturing Practices at Major Suppliers
  • 15.8.1 Process gas abatement
  • 15.8.2 Water recycling and reuse
• 15.9 Market and Regulatory Outlook 2026-2037
  • 15.9.1 Carbon-related regulatory tightening
  • 15.9.2 Embodied-carbon-conscious procurement
  • 15.9.3 The carbon-aware AI compute frontier

16 MARKET FORECASTS: GENAI HARDWARE 2026-2037

• 16.1 Forecast Methodology and Framework
• 16.2 Total GenAI Hardware Market - Base Case Forecast
• 16.3 Bull/Base/Bear Scenarios at Aggregate Level
• 16.4 AI Accelerator Silicon Sub-Segment Forecast
  • 16.4.1 Merchant vs. captive ASIC share trajectory
  • 16.4.2 China sovereign-stack AI silicon trajectory
• 16.5 HBM and Memory Sub-Segment Forecast
• 16.6 Advanced Packaging Sub-Segment Forecast
• 16.7 Photonics Packaging Sub-Segment Forecast
• 16.8 Thermal Management Sub-Segment Forecast
• 16.9 Power Delivery Sub-Segment Forecast
• 16.10 Networking and Optical Sub-Segment Forecast
• 16.11 Datacenter Construction Supply Chain Sub-Segment Forecast
• 16.12 Edge AI Silicon Sub-Segment Forecast
• 16.13 Regional Capture Forecast
• 16.14 Customer Tier Forecast
• 16.15 Key Forecast Risks and Sensitivities
  • 16.15.1 The CapEx normalisation risk
  • 16.15.2 The Taiwan concentration risk
  • 16.15.3 Model training economics
  • 16.15.4 Chinese sovereign-stack acceleration
  • 16.15.5 Power infrastructure constraints

17 STRATEGIC OUTLOOK

• 17.1 The Five Defining Themes of the GenAI Hardware Decade
• 17.2 The Choke-Point Map
• 17.3 The Strategic Investment Framework
• 17.4 M&A Landscape and Strategic Consolidation
  • 17.4.1 Photonics consolidation
  • 17.4.2 Memory and HBM consolidation
  • 17.4.3 Equipment and tools consolidation
  • 17.4.4 AI silicon start-up consolidation
  • 17.4.5 Forward M&A trajectory through 2030
• 17.5 Sensitivity Analysis
• 17.6 Strategic Implications by Stakeholder
  • 17.6.1 For AI accelerator silicon designers
  • 17.6.2 For hyperscalers and AI cloud operators
  • 17.6.3 For memory manufacturers
  • 17.6.4 For foundries
  • 17.6.5 For OSATs and substrate suppliers
  • 17.6.6 For thermal and power infrastructure suppliers
  • 17.6.7 For photonics packaging participants
  • 17.6.8 For governments and policymakers
• 17.7 What Could Change This Forecast
  • 17.7.1 Upside surprises
  • 17.7.2 Downside surprises
  • 17.7.3 Structural rather than cyclical risk

18 APPENDIX

• 18.1 Forecast Methodology
  • 18.1.1 Unit volume forecast construction
  • 18.1.2 ASP and content-per-unit forecast construction
  • 18.1.3 Scenario construction
  • 18.1.4 Cross-validation
• 18.2 Definitions and Terminology
  • 18.2.1 AI accelerator silicon categories
  • 18.2.2 Memory technology categories
  • 18.2.3 Packaging terminology
  • 18.2.4 Photonics terminology
  • 18.2.5 Thermal terminology
  • 18.2.6 Power terminology
  • 18.2.7 Networking terminology
  • 18.2.8 Geographic and customer terminology
• 18.3 Abbreviations
• 18.4 Sources and References
  • 18.4.1 Primary research
  • 18.4.2 Company financial disclosures
  • 18.4.3 Industry-association and government statistics
  • 18.4.4 Cross-reference industry reports
  • 18.4.5 Technical and scientific literature
• 18.5 Forecast Scope, Limitations, and Disclaimers
  • 18.5.1 Forecast scope
  • 18.5.2 Forecast limitations
  • 18.5.3 Disclaimers
• 18.6 Detailed Year-by-Year Forecast Outputs